Unbranded Dual Jk Flip Flop
DUAL JK FLIP FLOP High speed CMOS recommend for High speed CMOS recommend for all new designs. Static sensitall new designs. Static sensitive. Required light decoupling (0.1µF per 20 ICs) With 75-8g (0.1µF per 20 ICs) With 75-80% power reduction compared to 0% power reduction compared to standard Schottky. FEATURES Tri-S standard Schottky. Octaltate Quad D Register Transparent Latch (3 State) PACKAGE CONTENTS 1 x Dual Jk Flip Flop
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